1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the channel and the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide the gate. Thereafter, the gate provides an implant mask during the implantation of source and drain regions, and the implanted dopants are driven-in and activated using a high-temperature anneal that would otherwise melt the aluminum.
An important parameter in IGFETs is the threshold voltage (V.sub.T), which is the minimum gate voltage required to induce the channel. In general, the positive gate voltage of an N-channel device must be larger than some threshold voltage before a conducting channel is induced, and the negative gate voltage of a P-channel device must be more negative than some threshold voltage to induce the required positive charge (mobile holes) in the channel. There are, however, exceptions to this general rule. For example, depletion-mode devices already have a channel with zero gate voltage, and therefore are normally on. With N-channel depletion-mode devices a negative gate voltage is required to turn the devices off, and with P-channel depletion-mode devices a positive gate voltage is required to turn the devices off.
If the source and body of an IGFET are tied to ground, the threshold voltage can be calculated as follows: EQU V.sub.T =.phi..sub.ms -2.sub..phi.f -Q.sub.tot /C.sub.ox -Q.sub.BO /C.sub.ox -.DELTA.V.sub.T ( 1)
where .phi..sub.ms is the work-function difference between the gate material and the bulk silicon in the channel, .sub..phi.f is the equilibrium electrostatic potential in a semiconductor, Q.sub.tot is the total positive oxide charge per unit area at the interface between the oxide and the bulk silicon, C.sub.ox is the gate oxide capacitance per unit area, Q.sub.BO is the charge stored per unit area in the depletion region, and .DELTA.V.sub.T is a threshold lowering term associated with short-channel effects. Expressions have been established for these various quantities in terms of doping concentrations, physical constants, device structure dimensions, and temperature. For example, the work-function difference .phi..sub.ms varies as a function of the doping concentration in a polysilicon gate. Therefore, the threshold voltage depends on the doping concentration in the polysilicon gate.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to spacers adjacent to the gate. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity heavily doped region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics.
In the event a polysilicon gate is doped solely by the implant steps that provide source/drain doping, in some instances the doping concentration in the polysilicon gate may not be sufficient to provide the desired threshold voltage. Techniques for increasing the doping concentration in a polysilicon gate independently of source/drain doping are known in the art. For instance, the polysilicon layer that is subsequently etched to form the gate can be doped in situ as deposition occurs. In situ doping involves adding dopant gases such as diborane and phosphine to the chemical vapor deposition gases. Although combining doping and deposition in one step may appear simple, the control of film thickness, dopant uniformity, and deposition rate is greatly complicated by the addition of the dopant gases. Moreover, physical properties of the film such as grain size and grain orientation are affected. Alternatively, the polysilicon layer can be doped by solid phase diffusion. An advantage of this approach is its ability to introduce very high concentrations of the dopant in the polysilicon layer, however, a very high temperature is required and the potential exists for increasing the surface roughness. Furthermore, maximally doped polysilicon films are typically more important for other applications such as high value load resistors used in static memory, and doping studies. As yet another approach, the polysilicon layer can be doped by ion implantation. The implant energy is usually selected so that the peak concentration of the dopant is near the center of the polysilicon layer. This approach has the advantage of precise control over the dopant dose, however, an additional implant step becomes necessary.
Accordingly, a need exists for an improved method of making an IGFET that provides a polysilicon gate with the desired doping concentration without requiring additional implant steps.